Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
Description of the Background Art
As a structure of an LDMOS (Laterally Double-diffused Metal Oxide Semiconductor) transistor, a structure described in Japanese Patent Laying-Open No. 2009-130021 is known.
The LDMOS transistor described in patent document 1 has a substrate, an n− active layer, an n− drift layer, a p− body diffusion layer, an n+ drain region, an n+ source region, a p+ diffusion layer, a gate oxide layer, a gate polycide electrode, and a LOCOS (Local Oxidation Of Silicon) oxide film.
The substrate has a first surface and a second surface. The n− drift layer and the p− body diffusion layer are disposed on the n− active layer. The p− body diffusion layer is sandwiched by the n+ source region and the n− drift region. The n+ drain region is disposed in the n− drift region in contact with the first surface. The n+ source region is disposed in the p− body region in contact with the first surface. The p+ diffusion layer is disposed in the n− drift region in contact with the first surface.
The LOCOS oxide film is disposed between the p+ diffusion layer and the n+ drain region. The p+ diffusion layer is formed toward the second surface to reach a position deeper than the LOCOS oxide film. The gate oxide layer is disposed on the first surface between the p+ diffusion layer and the n+ source region. The gate polycide electrode is disposed on the gate oxide layer.
As structures of other LDMOSFETs, structures described in Japanese Patent Laying-Open Nos. 2011-181709, 2014-107302, and 2015-023208 are known.